Semiconductor-on-insulator (SOI) technology was first commercialized in the late 1990s. The defining characteristic of SOI technology is that the semiconductor region in which circuitry is formed is isolated from bulk substrate by an electrically insulating layer. This insulating layer is typically silicon-dioxide. The reason silicon-dioxide is chosen is that it can be formed on a wafer of silicon by oxidizing the wafer and is therefore amenable to efficient manufacturing. The advantageous aspects of SOI technology stem directly from the ability of the insulator layer to electronically isolate the active layer from bulk substrate. As used herein and in the appended claims, the region in which signal-processing circuitry is formed on an SOI structure is referred to as the active layer of the SOI structure.
SOI wafer 100 is shown in FIG. 1. The wafer includes substrate layer 101, insulator layer 102, and active layer 103. The substrate is typically a semiconductor material such as silicon. Insulator layer 102 is a dielectric which is often silicon-dioxide formed through the oxidation of substrate layer 101. Active layer 103 includes a combination of dopants, dielectrics, polysilicon, metal layers, passivation, and other layers that are present after circuitry 104 has been formed therein. Circuitry 104 may include metal wiring; passive devices such as resistors, capacitors, and inductors; and active devices such as transistors. As used herein and in the appended claims, the “top” of SOI wafer 100 references top surface 105 while the “bottom” of SOI wafer 100 references bottom surface 106. This orientation scheme persists regardless of the relative orientation of SOI wafer 100 to other frames of reference, and the removal of layers from, or the addition of layers to SOI wafer 100. Therefore, active layer 103 is always “above” insulator layer 102. In addition, a vector originating in the center of active layer 103 and extending towards bottom surface 106 will always point in the direction of the “back side” of the SOI structure regardless of the relative orientation of SOI wafer 100 to other frames of references, and the removal of layers from, or the addition of layers to SOI wafer 100.
Semiconductor devices are most commonly produced in bulk on large wafers comprising many individual devices which are called die. Bulk processing is one of the reasons semiconductor manufacturing is characterized by minimal variable cost production. Dice are not processed individually until very late in the overall manufacturing process. The process by which the individual dice are taken from the wafer is called singulation. Standard singulation methods include wafer saw, scribe and break, laser cutting, and other methods. All of these singulation methods have the potential to cause stress on the individual die, and could also possibly cause defects in any resultant device. SOI devices are particularly susceptible to these types of manufacturing errors because the active layer is thin, and therefore less able to protect the contained circuitry as compared to the thicker bulk substrates used in traditional semiconductor devices. Stress induced during singulation may cause plastic deformation of the active circuitry and wafer warpage which may result in silicon crystal defects such as slip and dislocation generation. These conditions will significantly decrease the electrical performance and product yield of a resulting device.
Various methods exist to provide stability to circuitry during processing. A prominent approach involves the attachment of a support structure to the wafer before individual die on the original wafer are thinned or singulated. For example, a supporting handle wafer may be attached to the active layer to add support to the active layer during singulation or thinning. This handle wafer will usually remain on the active layer and form a part of the final device. Another approach to the problem of providing stability to traditional semiconductor devices during thinning is to selectively thin a framework of wafer material in a border around a subset of die. This approach allows the substrate of individual devices to be thinned while still being supported in groups for further processing.